Lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the mask may contain a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g., comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus, commonly referred to as a step-and-scan apparatus, each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction. Since, in general, the projection system will have a magnification factor M (generally >1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic devices as described herein can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
In a manufacturing process using a lithographic projection apparatus, a mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g., an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc.
For the sake of simplicity, the projection system may hereinafter be referred to as the “optics;” however, this term should be broadly interpreted as encompassing various types of projection systems, including refractive optics, reflective optics, and catadioptric systems, for example. The radiation system may also include components operating according to any of these design types for directing, shaping or controlling the projection beam of radiation, and such components may also be referred to below, collectively or singularly, as a “lens.” Further, the lithographic apparatus may be of a type having two or more substrate tables (and/or two or more mask tables). In such “multiple stage” devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic apparatus are described, for example, in U.S. Pat. No. 5,969,441, incorporated herein by reference.
The photolithographic masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way. A critical dimension of a circuit can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes. Thus, the CD determines the overall size and density of the designed circuit.
Due to an accuracy requirement for optical proximity correction (OPC) at very low k1 (<0.4), more accurate representation of the performance of the exposure tool in simulations has become critical to accommodate the reduction of device pattern dimensions. To satisfy such a requirement, one of the effects required to be taken into account in the simulation process is the flare occurring in the imaging process. Flare, which is unwanted scattered light arriving at a wafer, is caused by anything that forces the light to travel in a non-ray trace direction. The flare increases the background intensity and results in reduction in the image contrast, thereby degrading the pattern fidelity and CD uniformity. The amount of flare experienced by any given feature is a function of both the local environment around that feature (short-range flare) and the total amount of energy going through the lens (long-range flare). The short-range flare can degrade image contrast and, if varied across the field, can contribute to across-field CD variation. For example, imperfection in a lens such as surface roughness affects short-range flare.
FIG. 1 shows how short-range flare can undesirably reduce the contrast of an image, which will in turn negatively effect the resist profile. FIG. 2 shows the CD-through-pitch behavior of an illumination system with and without short-range flare. These figures show that when the flare effect is included in the simulation, the contrast of the resulting image is reduced. Accordingly, if optical proximity correction (OPC) rules are generated from simulation results that do not take flare into account, the actual imaging results may not satisfy the imaging requirements. Indeed, as minimum CD requirements continue to be reduced, it will become increasingly necessary to have a simulation model that accurately compensates for the effects of flare.
Therefore, it is an object of the present invention to provide a method that accurately accounts for short-range flare in the simulation process so as to obtain more accurate simulation result.